Apr 19, 2018
**Job Description** Job Description The Scalable Performance CPU group is looking for a high-energy and passionate engineer to help develop state of the art products fueling Intel's growth in the data center. 'We are seeking an experienced SoC/IP RTL design engineer to join a diverse team designing products for the High Performance Computing, AI and Custom CPU markets. In this specific role, you will be part of a multi-functional team responsible for architecting, developing and deploying FPGA prototypes for next-gen SoC/ASIC architectures to enable validation of HW/SW architecture, interactions and performance. Responsibilities : + Collaborate with HW/SW architects to gather prototype requirements and define architecture. + Define Micro-architecture of logic blocks while making power/performance/area trade-offs and write detailed specifications. + Develop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure & FPGA implementation. + Collaborate with design verification team to develop a detailed verification test-plan and support simulation bring-up/debug and bug fixes. + Collaborate with HW/SW engineers to enable lab bring-up/debug of prototype. **Qualifications** Minimum qualifications: + BS degree in ECE or CS Engineering with 8 years of industry experience OR a MS degree in ECE or CS Engineering with 6 years of industry experience. + Experience with SoC/ASIC/FPGA design methodology. + Experience with RTL design using Verilog/System Verilog. + Experience in debug, troubleshooting, and failure analysis investigation. + Experience with FPGA designs on Intel/Xilinx devices , tools and prototyping platforms HAPS/Protium. + Expertise in one of the following domains PCIE Memory subsystem architecture and cache coherency protocols SoC Fabric/Interconnect design CPU/Accelerator design. + Experience with scripting/firmware/system-software development. + Experience with Post-Si lab debug/bringup. + Strong collaboration and interpersonal skills. **This is an Intel Federal Position** + This position involves work on a U.S. Government contract which may impose certain security requirements. + The government may require that you certify your citizenship status. + If you are not a U.S. citizen, the government may require you to pass a security check before you can be approved to work on the project. + Please note that any offer by Intel for this position is conditioned upon meeting and/or passing the U.S. Government's security check requirements should the government impose these requirements. **Inside this Business Group** The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering. **Other Locations** US, Oregon, Hillsboro **Posting Statement.** Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
Intel Santa Clara, CA, USA